1. Field of the Invention
The present invention generally relates to memory-effect plasma display panels generally having two parallel plates, each supporting electrode networks and between which is present a gas causing luminous discharges at regions of intersection between the electrodes of the plates and, more specifically, to a circuit for controlling one of the electrode networks of the panels, used both to address pixels and to maintain an excitation of the pixels.
2. Description of the Related Art
FIG. 1 generally and very schematically shows the structure of a plasma display panel 1 (PDP) of the type to which the present invention applies. Two parallel plates designated by general reference 2 each support electrodes generally perpendicular from one plate to the other and parallel to each other on a same plate. Each line L of the display panel is defined by two parallel electrodes 3 and 4 and each column C of the display panel is defined by an electrode 5 in the other direction supported by the other plate. The intersection of a line L and of a column C defines a pixel P of the screen. To light a pixel, a luminous discharge is organized between electrodes 3 and 4 of a line L, addressed by the corresponding column 5.
The control of screen 2 is performed by means of column electrode control circuits 6 (COL DRV) and line electrode control circuits 7 (SCAN DRV), the latter being connected to power supply circuits 8 (PW CT). Circuits 6, 7, and 8 are controlled and synchronized by a unit 9 (CU), generally a microcontroller or a circuit in wired logic.
The present invention more specifically relates to the control of electrodes 3 and 4 of lines of a plasma display panel.
FIG. 2 schematically shows an example of a conventional circuit for controlling electrodes 3 and 4 of a line of a screen 2 such as shown in FIG. 1. The circuits shown in FIG. 2 are, in FIG. 1, contained in blocks 7 and 8. The circuit of FIG. 2 is based on the use of switches operating in all or nothing, i.e., either on or off, to bring, onto one of the electrodes (for example, electrode 3) of the considered line, different voltage levels at different operating phases. For simplification, the control signals generated by unit 9 have not been detailed. Further, the different switches have been schematically shown, most often in parallel with a reverse voltage hold diode.
In practice and as illustrated in FIG. 3, which shows an example of a switch used in the circuit of FIG. 2, each switch is formed of an N-channel MOS transistor MN having its intrinsic diode D connecting the source s to the drain d, forming the diode of the involved switch. Gate g of MOS transistor MN forms the switch control electrode. The switches may also be insulated-gate transistors (IGBT) or others.
The control circuit of each electrode 3, contained in block 7 (scan driver) of FIG. 1, is formed of two switches Tu and Td in series between two terminals 11 and 12 and having their junction point 13 directly connected to electrode 3 (conductive line of screen 2). The other electrode 4 parallel to electrode 3 and belonging to the same line is generally connected to a circuit (not shown) of provision of a reference voltage. Each switch Tu, Td is in parallel with a diode Du, Dd respectively, the respective anodes of diodes Du and Dd being connected to terminals 13 and 12. Switches Tu and Td are used to select that electrode 3 of the display panel lines that will receive the different voltages to be applied thereto. For simplification, a single circuit 7 has been shown in FIG. 2. In practice, all the circuits 7 (as a variation, groups of circuit 7) of screen 2 have their respective terminals 11 and 12 interconnected to a common power supply circuit 8.
The supply circuit 8 includes a so-called Weber-type energy recovery stage 20 intended to impose a voltage on the line electrode 3 by carrying off excess charges or by bringing missing charges on electrode 3 in a so-called sustain operating phase. The recovery stage 20 mainly includes an inductive element L connecting, by a bidirectional switch 22, an electrode of a capacitor Cr to an output terminal 21 of the stage, connectable to electrode 3. The switch 22 is typically formed of two switches T22 and T22′ in antiparallel and each in series with a diode D22, respectively D22′. The output terminal 21 of the recovery stage 20 is connected, by a switch Ts, to a terminal 23 of application of a positive voltage Vs and, by a switch Ts′, to a terminal 24 of application of a reference voltage Vref (typically, the ground). Each switch Ts and Ts′ is in parallel with a diode Ds, respectively Ds′, the respective anodes of diodes Ds and Ds′ being connected to the output and ground terminals 21 and 24, respectively.
The output terminal 21 of the recovery circuit 20, and thus inductance L providing or absorbing a current, is connectable to the input terminals 11 of all scan driver circuits 7 by a same switch T1 in parallel with a diode D1 having its anode connected to node 21.
A stage of prebiasing or precharge of electrodes 3 is formed of a switch Tp connecting a terminal 26 of application of a positive voltage Vp (greater than voltage Vs) to the input terminal 11, with switch Tp being in parallel with a diode Dp having its anode connected to input terminal 11 (across all circuits 7).
An addressing step is formed of a capacitor Cs charged, via a diode Dsc, with an addressing voltage Vsc applied on a terminal 28, the anode of diode Dsc being connected to terminal 28 and its cathode being directly connected to a first electrode 29 of capacitor Cs. A switch T6 connects electrode 29 to input terminals 11 and second electrode 30 of capacitor Cs is connected directly to input terminals 12 of the scan driver circuits 7. For simplification, the parasitic diode of the MOS transistor forming switch T6 has not been shown, since said diode is not used in this assembly.
An addressing reference voltage Vadd is generally applied to input terminals 12 by means of a switch T4 connecting terminals 12 to a terminal 32 of application of voltage Vadd (negative with respect to ground), a diode D4 being in parallel with switch T4, its anode being connected to terminal 32.
In certain cases, an erasing voltage Ver, different from reference addressing voltage Vadd, is applied by an erasing stage (in dotted lines in FIG. 2) formed of a switch T5 in parallel with a diode D5 connecting terminals 12 to a terminal 33 of application of voltage Ver, intermediary between voltage Vadd and reference voltage Vref, the anode of diode D5 being connected to terminal 33 of application of voltage Ver.
Finally, a switch T3 interconnects all the terminals 11 and 12, no diode has been shown in parallel with this switch since, even if it is present with the MOS transistor forming the switch, it is not used herein.
A control circuit such as illustrated in FIG. 2 is described, for example, in international patent application WO 03/102907.
FIGS. 4 and 5 shows an example of timing diagrams illustrating the operation of the circuit of FIG. 2. They respectively show timing diagrams of voltage V3 present on an electrode 3 of a line during a display sub-frame, and the respective off or on states of the different switches. In FIG. 5, an indifferent state of a switch has been illustrated by a cross during the considered period. In the representation of FIGS. 4 and 5, the presence of an erasing voltage Ver different from addressing voltage Vadd is assumed. If the two voltages are confounded, the controls of switches T4 and T5 are accordingly adapted.
Electrode 3 is initially assumed to be at voltage Vs.
In a so-called prebiasing or precharge phase I (from a time t1), switch T1 is off, as well as switches T4, T5, T6. Switches T3 and Tp are on so that voltage Vp is applied to electrode 3 by diode Dd. During this phase I, switch Tu is off and switch Td is on. Switches Ts and Ts′ are either both off, or in inverted states with respect to each other. The same occurs for switches T22 and T22′. The function of the prebiasing phase is to excite the cells to pre-excite the gas contained in the screen to lower the addressing voltage under which the discharge will be performed afterwards. Typically, voltage Vp is on the order of 400 volts.
At the end (time t2) of the prebiasing phase, a so-called stabilization phase II starts. During phase II, switch Tp is off and will remain so until the beginning of a next sub-frame (time t1′). Switches T4, T5, and T6 remain open. Switch T1 is on. This phase aims at bringing the voltage of input terminal 11 to level Vs. Accordingly, switch Ts is on while switch Ts′ is off. Switch T3 for example remains on, but its state is of no importance during this phase. The states of switches Tu and Td are indifferent, as well as the states of switches T22 and T22′.
At the end (time t3) of stabilization phase II, a so-called erasing phase III aiming at bringing electrode 3 to point Ver starts. In the shown example, erasing level Ver is assumed to be lower than level Vref (ground). In other cases, this erasing voltage may be equal to ground. At time t3, switch T5 is on. Switch T1 is off to isolate recovery stage 20 from the rest of the circuit, and switches T4 and T6 remain off. Switches T3 and Tu are off and switch Td is on. The discharge of the voltage of electrode 3 down to level Ver is performed by means of switch Td.
Phases II and III of erasing of the prebiasing result in suppressing the charges to avoid undesired start-ups. The erasing ramp of phase III is obtained by a current generator series-connected with switch T5 (for example, by a resistor).
At an end time t4 of the erasing phase, a so-called addressing phase IV which aims at bringing an addressing voltage corresponding to level Vsc or to level Vadd on electrodes 3, according to the respective states of transistors Tu and Td of their addressing circuit 7, starts. During this phase, switch T1 is indifferently off or on and switches T4 and T6 are on to bring respective levels Vsc and Vadd onto terminals 11 and 12. Switch T3 is off to separate terminals 11 and 12. Switch T5 is off.
Period tIV in phase IV during which switch Tu is off and switch Td is on depends on the rank of the line in the line group or in the display panel.
At a time t5 corresponding to the end of the addressing phase, a so-called sustain phase V during which a pulse train of constant duty cycle and of amplitude Vs is applied on terminal 23 starts. During this phase, switch T1 is on to bring the pulses onto circuits 7, and switch T3 is also on, while switches T4, T5, and T6 are off to isolate the addressing and erasing stages. Switch Tu is off and switch Td is on. In sustain phase V, recovery stage 20 is used to ease the charge of electrodes 3 to level Vs and ease the discharge of the same electrodes in the respective low levels of the pulses. The turning on and off of switches Ts and Ts′ alternate at the rate of the pulses of level Vs to be applied to terminal 11. Switches T22 and T22′ are, for example, alternately turned off and on synchronously with the turning off and on of switches Ts and Ts′.
At the end (time t6) of the sustain phase, electrode line 3 is brought to erasing voltage Ver, in a so-called initialization phase VI carrying on until time t1′ of beginning of the next sub-frame. In phase VI, switch T1 remains on while switches T4 and T6 remain off, switch T5 is on and switch T3 is off. Switches Ts, Ts′, T22, and T22′ are off. The discharge of electrode 3 is ensured by the turning-on of switch Td, the state of switch Tu being off.
A disadvantage of the circuit of FIG. 2 is linked to the significant current flowing through transistors T1 and T3 during phases II, V, and VI in which the recovery stage is used. This imposes using transistors T1 and T3 of large dimensions, and thus expensive.